Authors: Milad Bahadori and Kimmo J¨arvinen
Abstract - A multitude of privacy enhancing technologies have been presented recently to solve privacy problems of contemporary services utilizing cloud computing. Many of them are based on additively homomorphic encryption that allows computation of additions on encrypted data. The main technical obstacles for adaptation of privacy enhancing technologies in practical systems are related to performance overheads compared to current privacy-violating alternatives. In this paper, we present a HW/SW codesign for programmable SoCs that is designed for accelerating applications based on Paillier encryption. Our implementation is a microcode based multi-core architecture which is suitable for accelerating various privacy enhancing technologies using additively homomorphic encryption with large integer modular arithmetic. We instantiate the implementation in a Xilinx Zynq- 7000 programmable SoC and provide performance evaluations in real hardware. We also investigate its efficiency in a high end Xilinx UltraScale+ programmable SoC. We evaluate the implementation with two target use cases that have relevance in privacy enhancing technologies: privacy-preserving computation of squared Euclidean distances over encrypted data and multi-input functional encryption for inner products. Both of them represent the first hardware acceleration results for such operations and, in particular, the latter one is among the very first published implementation results of functional encryption on any platform.
